(1) Field of the Invention
This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to an apparatus and method for planarizing a sub-micron integrated circuit device using spin-on materials, such as SOG (Spin-On-Glass).
(2) Description of Related Art
The complexity of present-day integrated circuits requires that the devices on silicon wafer substrates shrink to sub-micron dimensions and the circuit density increases to several million transistors per die. In order to achieve these requirements smaller and smaller feature sizes are needed for both width and spacing of features. Furthermore, as wiring densities in semiconductor circuit chips increase, multiple wiring levels are required to achieve interconnection of the devices, and planarization of the interlevel dielectric becomes a critical step in the fabrication process. Planarized dielectric layers must be formed between metal layers of an integrated circuit in order to achieve good metallization step coverage of the interconnnect metal lines. Also, planarization is necessary to facilitate masking and etching operations. A planarized surface provides a constant depth of focus across the surface for exposing patterns in lithographic layers.
Spin-on dielectric materials, such as SOG (Spin-On-Glass), have been used as the insulating layer between successive interconnection layers. However, complete planarization has not been possible with the application of a single SOG layer. Processes which resort to application of multiple layers of SOG are costly and are subject to higher defect levels. Also, dielectric layers composed of multiple layers are subject to delamination due to poor adhesion between layers. Additional attempts to achieve improved planarization have combined SOG with CMP (Chemical Mechanical Polishing) processes or with plasma etchback processes, but such process combinations suffer from the disadvantages of high expense, low product throughput, and process complexity.
Numerous improvements to methods of forming planarized dielectric layers utilizing SOG have been invented. For example, U.S. Pat. No. 5,312,512 entitled "Global Planarization using SOG and CMP" granted May 17, 1994 to Derryl D. J. Allman et al describes a multiple step process which uses the combination of SOG, etching away higher portions of the SOG layer, and CMP (Chemical Mechanical Polishing) to produce a planarized dielectric surface.
And, U.S. Pat. No. 5,302,233 entitled "Method For Shaping Features of a Semiconductor Struture Using Chemical Mechanical Planarization (CMP)" granted Apr. 12, 1994 to Sung C. Kim et al describes a method of planarizing a dielectric layer, which includes a CMP step using a relatively soft and conforming polishing pad. CMP with the soft pad allows the topography to be contoured. After contouring the topography, additional dielectric material is deposited and planarization is completed by further CMP with a relativley hard polish pad.
Also, U.S. Pat. No. 5,454,871 entitled "SOG Coated Apparatus To Solve SOG Non-Uniformity in the VLSI Process" granted Oct. 3, 1995 to Yung-haw Liaw et al describes an apparatus for applying SOG under controlled humidity conditions. By controlling the humidity during application of SOG the integrity of multiple layers of SOG is improved.